With the continuous development of the integrated circuit (IC) manufacturing technology, the critical dimension of MOS transistors has become smaller and smaller. To reduce the parasitic capacitance of the gates of the MOS transistors; and to increase device speed, a stacked gate structure with a high dielectric constant (high-K) gate dielectric layer and a metal gate, i.e., a high-K metal gate (HKMG) structure, has been applied in the MOS transistors. To prevent the metal material of the metal gate of the HKMG structure from affecting other structures of the MOS transistors, a gate-last process is often used to form the HKMG structure.
The gate-last process for forming the HKMG structure includes providing a semiconductor substrate; and forming a dummy gate structure on the semiconductor substrate. The dummy gate structure includes a gate dielectric layer formed on the semiconductor substrate and a dummy gate formed on the gate dielectric layer; and source/drain regions are formed in the semiconductor substrate at both sides of the dummy gate structure. Further, the gate-last process also includes forming a first dielectric material layer covering the dummy gate structure on the semiconductor substrate; and planarizing the first dielectric material layer by a chemical mechanical polishing (CMP) process using the top surface of the dummy gate structure as a stop layer to form a first dielectric layer. The top surface of the first dielectric layer levels with the top surface of the dummy gate structure.
Further, the gate-last process also includes removing the dummy gate structure to form a trench; and forming a high-K material layer on the side and bottom surfaces of the trench and the surface of the first dielectric layer. Further, the gate-last process also includes forming a metal layer on the high-K material layer, and removing portions of the high-K material and the metal layer on the first dielectric layer to form a high-K gate dielectric layer on the side and bottom surfaces of the trench, and a metal gate layer on the high-K gate dielectric layer and in trench.
Further, the gate-last process also includes forming a second dielectric layer on the metal gate layer, the high-K gate dielectric layer and the first dielectric layer; and etching the second dielectric layer and the first dielectric layer to form a first through-hole to expose the surface of the source region or the drain region; and etching the second dielectric layer to form a second through-hole to expose the surface of the metal gate layer. Further, the gate-last process also includes filling a metal material in the first through-hole to form a first conducive via; and filling a metal material in the second through-hole to form a second conductive via.
However, the reliability and the stability of the fabrication process of the HKMG structure may need further improvements. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.